The Verigy 93K tester is widely used in the semiconductor industry for a variety of applications, including:
Allows different pin groups to run at completely independent frequencies, facilitating multi-port testing. Key Instrumentation Classes
It collects massive amounts of data to help manufacturers improve their "yield" (the percentage of chips that actually work). 3. Impact on the Digital World
I can provide targeted code snippets, specific API calls, or tailored hardware debug procedures. Share public link
You must map the tester pins to the physical pins on your chip. This is done in a configuration file. Levels and Timing Set the high and low voltages for the signals. verigy 93k tester manual
Signals like START_TEST , END_TEST , and BIN_RESULTS are transmitted between the tester and the handler using hardware interfaces (TTL/GPIB) or network-based soft-protocols (like Advantest's standard driver interfaces). Multi-Site (Parallel) Testing Optimization
Incorrect pin mapping is the #1 cause of “DUT contact failure.” The manual provides:
Dust accumulation in air filters or low fluid levels in the external chiller can trigger automatic thermal shutdowns. Check the hardware status panel for airflow and temperature errors.
Utilizes the independent sequencer capabilities of the Scale architecture to run distinct functional patterns across independent groups of devices simultaneously. Data Logging and Yield Analysis The Verigy 93K tester is widely used in
A detailed breakdown of the software environment used to control the tester, including pin configuration, level setup, and timing. SmarTest 7 Digital Training: Documentation for the Smart Scale
A graphical tool that visualizes digital waveforms, drive edges, and receive strobe windows in real-time. It is invaluable for debugging setup and hold time issues.
: Explains the classic, object-oriented workbook structure based on ASCII configuration files.
An automated software utility that aligns signal arrival times across all pins. It compensates for internal board trace propagation delays, cable variances, and temperature drifts. Impact on the Digital World I can provide
Covers hardware properties, test system components, start-up/shutdown, and device power supply (DPS).
The 93K is a modular, scalable tester. A manual for a base configuration (e.g., 128 digital channels, 4 PS1600 power supplies) looks vastly different from a system with 1024 channels, RF modules, and high-speed optical I/O.
The manual includes a comprehensive list of error codes. Running the "Check Health" diagnostic tool is the first step in troubleshooting any hardware failure, such as a blown fuse or a malfunctioning pin electronics (PE) card. Developing a Test Program
The digital subsystem operates on a "tester-per-pin" architecture. Each digital channel features independent timing generators, algorithmic pattern generators (APGs), and per-pin parametric measurement units (PPMUs).